Controls & Automation
Smart Conveyor Sorting Simulation
A CODESYS and Factory I/O simulation focused on PLC sequence logic, OPC UA signal mapping and conveyor–turntable coordination.
- Project type
- Personal simulation
- My role
- PLC sequence development and simulation integration
- Period
- Aug 2026

CODESYS runtime connected and running
The supplied setup screenshot shows the SoftPLC connected and the application in RUN. It establishes the runtime baseline; it does not by itself demonstrate conveyor motion or completion of the sorting sequence.
View source ↗Overview
This local simulation links CODESYS Control Win to a Factory I/O conveyor scene. I worked on the signal mapping and Structured Text sequence logic coordinating sensors, conveyors, a turntable and transfer operations.
The scene and initial PLC sample came from the Factory I/O CODESYS OPC UA tutorial. My documented changes separate the simulation addresses from the control logic and replace multiple sequence-state Boolean variables with one explicit state machine.
Architecture & I/O boundary
CODESYS Control Win acts as the SoftPLC and exchanges signals with Factory I/O over OPC UA. Factory I/O addresses are confined to the input and output mapping boundary, keeping the sequence logic independent of those addresses.
Input mappings translate FIO.i variables into internal feedback variables. The logic produces internal actuator commands, which are mapped back to FIO.o outputs.
Documented control path
Factory I/O sensors
→ PLC input mapping
→ Internal feedback
→ Sequence / machine logic
→ Actuator commands
→ PLC output mapping
→ Factory I/O actuatorsSequence control
A single E_SequenceState variable represents the current turntable stage. The documented sequence progresses through loading, rotation to unload, discharge and return to the loading position before returning to idle.
Separating feedback from actuator commands makes each stage easier to inspect. My project work also included diagnosing retained-state and timing faults and verifying the corrected end-to-end operating cycle.
Turntable state sequence
SEQ_IDLE
→ SEQ_LOADING
→ SEQ_ROTATE_TO_UNLOAD
→ SEQ_DISCHARGING
→ SEQ_RETURN_TO_LOAD
→ SEQ_IDLEA single sequence-state variable makes the active stage explicit, instead of requiring several independent Boolean state flags to remain consistent.
Connection & mapping diagnosis
The first integration problem was a mismatch between the runtime security settings and the sample's anonymous OPC UA connection. After correcting the local simulation configuration, Factory I/O could browse all 18 FIO variables.
A subsequent null-reference error remained even though the variables were visible. I rebuilt the scene's saved I/O mappings against the current runtime; the error disappeared and the 18 signals could be exchanged without changing the PLC logic for these setup fixes.
Anonymous access was used only for this single-computer simulation. It is a limitation of the local setup, not a recommended access policy for a deployed control system.
Successful variable browsing isolated the second fault to the mapping layer. A running PLC and a working connection still require separate checks of the machine sequence.
Simulation validation
I checked the runtime, signal exchange and corrected operating cycle in simulation. The public evidence currently covers the runtime screenshot and written integration record. No physical PLC or production equipment was involved, and formal FAT-style documentation remains planned work.
SoftPLC runtime
- Expected behaviour
- The CODESYS application is connected and in RUN before integration checks.
- Actual result
- The supplied screenshot shows the connected application in RUN with zero build errors.
OPC UA mapping recovery
- Expected behaviour
- Factory I/O can browse the required variables and exchange the mapped inputs and outputs.
- Actual result
- The troubleshooting record reports all 18 variables visible and signal exchange restored after rebuilding the mappings.
End-to-end operating cycle
- Expected behaviour
- Sensors, conveyors, the turntable and transfer operations follow the corrected sequence.
- Actual result
- I verified the corrected cycle after signal-mapping, retained-state and timing fixes. The public evidence does not yet include a cycle recording or repeatable test log.
Outcomes & next development
The documented work establishes a working simulation connection, corrected I/O mapping, separate feedback and command layers, and a single state machine for the turntable sequence.
The key lesson was to diagnose runtime, endpoint, permissions, symbols, mappings and machine movement as separate checks. Restoring communications does not establish that the control sequence is correct.
Manual/Auto modes, operator requests, permissives and fault handling remain architecture placeholders in the project notes. Interlock validation, blockage or jam detection, fault recovery and FAT/SAT-style documentation are planned work, not demonstrated outcomes.